1. Field of the Invention
The present invention relates to a structure of a memory device and a fabrication method thereof. More particularly, the present invention relates to a structure of buried bit line of a memory device and a fabrication method thereof.
2. Description of Related Art
Memory device, by nature, is a semiconductor device used to store information and data. The storage of digital information is in unit of bit. Information is stored in a cell in the memory device. The specific location of each memory cell is known as an address. In other words, the memory cells in a memory device are arranged in an array, wherein a specific row and column constitutes a specified memory cell address. The memory cells on each row or each column are connected with a common conductive line.
Referring to FIG. 1, FIG. 1 is a schematic, cross-sectional view of a structure of a memory cell device according to the prior art.
Referring to FIG. 1, a conventional memory device comprises a substrate 10, a buried bit line 12, a gate oxide layer 16, an insulation structure 14 and a word line 18. The buried bit line 12 is disposed in the substrate, while the word line 18 extends above and across the buried bit line 12. Further, the gate oxide layer 16 is disposed on a surface of the substrate 10 to electrically isolate the word line 18 and the substrate 10. The insulation structure 14 is disposed above the buried bit line 12 to electrically isolate the word line 18 and the buried bit line 14.
Accompanying the increase of circuit integration and the miniaturization of device dimension, the linewidth of the buried drain region is also being scaled down. A narrower linewidth, however, would lead to its resistance to increase. Consequently, the current flow of the memory device is reduced and bit line loading would become too high. If the junction depth of the buried drain region is increased to resolve the problem of raised resistance at the linewidth, not only is the short channel effect generated, the problem of junction leakage also occurs. If a high concentration of dopants is used to form a shallow junction of the bit line to obviate the short channel effect and the junction leakage problem due to a deep junction, the overloading problem of the bit line remains unresolved because of the limitation of the solid-phase solubility. Further, in a conventional memory device, a bit line contact is required for every 32 bit lines or 64 bit lines to control the memory device. The formation of a bit line contact, however, is limited by the integration of the device. Lower the number of the bit line contact in order to increase the integration of the device is thus very important.